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test and measurement products 1 www .semtech.com edge629 1 ghz timing deskew and quad fanout element description featur es functional block diagram applications revision 3 / august 1, 2005 fmax 1 ghz independent falling edge adjust small footprint (10 mm x 10 mm) excellent timing accuracy very stable timing delays 5 ps resolution ecl, cmos compatible inputs memory test equipment data fanout channel deskew logic testers per pin deskew clock / signal fanout ? t ? t ? t coarse fine out0 / out0* in0 / in0* in / in* coarse fine out1 / out1* in1/ in1* coarse fine out2 / out2* in2 / in2* coarse fine out3 / out3* in3 / in3* sel / sel* ? t ? t ? t ? t ? t ? t ? t ? t ? t the edge629 is a monolithic timing delay and signal fanout solution manufactured in a high-performance bipolar pro- cess. in automatic test equipment (ate) applications, the edge629 buffers, distributes, and aligns timing signals across multiple channels (typically found inside memory test systems). it is also suitable for per pin deskew in logic testers. the edge629 supports: minimum pulse width = 330 ps with falling edge adjust disabled, 500 ps with falling edge adjust enabled net usable delay span 4.0 ns falling edge adjust 250 ps on board dacs to generate 5 ps resolution with a maximum operating frequency of 1 ghz, the edge629 is optimized for extremely high speed, high ac- curacy testers, particularly those aimed to test memory devices. the edge629 solves several difficult problems associated with aligning multiple timing signals because it can: delay very narrow pulses over a long timing span adjust the falling edge independently from the overall propagation delay maintain extreme timing accuracy for very narrow (sub-ns) pulses maintain tight timing accuracy over changes in frequency, duty cycle, and pattern.
2 test and measurement products edge629 ? 2005 semtech corp. rev. 3, 8/1/05 www.semtech.com pin description e m a n n i p# n i pn o i t p i r c s e d * n i / n i8 , 9. t u o n a f l a n g i s 4 : 1 r o f d e s u l a n g i s t u p n i l a i t n e r e f f i d * 0 n i , 0 n i * 1 n i / 1 n i * 2 n i / 2 n i * 3 n i / 3 n i 6 1 , 5 1 2 1 , 1 1 5 , 6 1 , 2 . t u o n a f l a n g i s 1 : 1 r o f d e s u s l a n g i s t u p n i l a i t n e r e f f i d * 0 t u o / 0 t u o * 1 t u o / 1 t u o * 2 t u o / 2 t u o * 3 t u o / 3 t u o 4 3 , 3 3 8 3 , 7 3 3 4 , 4 4 7 4 , 8 4 . s l a n g i s t u p t u o l a i t n e r e f f i d * l e s / l e s3 2 , 2 2 . e c r u o s l a n g i s t u p n i e h t t c e l e s o t d e s u s l a n g i s t u p n i l a i t n e r e f f i d i d s8 5. t u p n i a t a d l a i r e s k c6 5. i d s n i h c t a l o t d e s u k c o l c s c9 5. t c e l e s p i h c e t a d p u7 5. s r e t s i g e r y a l e d e h t s d a o l h c i h w t u p n i l a t i g i d e d o n a , e d o h t a c5 2 , 4 2. g n i r t s e d o i d l a m r e h t p i h c - n o n a f o s l a n i m r e t 3 - 0 p m o c1 6 , 2 6 , 9 1 , 0 2. s n i p n o i t a s n e p m o c p m a p o l a n r e t x e ) 3 - 0 ( _ l l a f _ c a d4 5 , 2 5 , 9 2 , 7 2 e b d l u o h s g n i h t o n ; y l n o s e s o p r u p t s e t r o f . s t u p t u o c a d t s u j d a e g d e g n i l l a f . s n i p e s e h t o t d e t c e n n o c ) 3 - 0 ( _ e n i f _ c a d3 5 , 1 5 , 0 3 , 8 2 d e t c e n n o c e b d l u o h s g n i h t o n ; y l n o s e s o p r u p t s e t r o f . s t u p t u o c a d y a l e d e n i f . s n i p e s e h t o t c c v, 6 2 , 4 1 , 3 1 , 4 , 3 , 5 4 , 0 4 , 6 3 , 5 3 , 1 3 5 5 , 0 5 , 6 4 . y l p p u s r e w o p e v i t i s o p e e v, 1 2 , 8 1 , 7 1 , 0 1 , 7 , 9 4 , 2 4 , 1 4 , 9 3 , 2 3 4 6 , 3 6 , 0 6 . y l p p u s r e w o p e v i t a g e n
3 ? 2005 semtech corp. rev. 3, 8/1/05 www.semtech.com test and measurement products edge629 pin description (continued) out3 out3* vcc3 vcc2 out2 out2* vee2 vee4 vcc4 vee1 out1* out1 vcc1 vcc0 out0* out0 in3* in3 vcc3 vcc2 in2* in2 vee2 in* in vee1 in1 in1* vcc1 vcc0 in0 in0* vee3 vee5 comp2 comp3 vee5 cs sdi update ck vcc5 dac_fall_3 dac_fine_3 dac_fall_2 dac_fine_2 vcc5 vee3 vee0 vee6 comp1 comp0 vee6 sel sel* cathode anode vcc6 dac_fall_0 dac_fine_0 dac_fall_1 dac_fine_1 vcc6 vee0 64 49 33 17 1 top view E629AXF 64 pin 10 mm x 10 mm tqfp
4 test and measurement products edge629 ? 2005 semtech corp. rev. 3, 8/1/05 www.semtech.com circuit description introduction the edge629 is a quad channel delay element with 2 basic operating modes: 1) fanout 1 signal in, 4 signals out 2) pass through 4 signals in, 4 signals out in all modes, each channel supports 3 delay functions: 1) coarse timing delay 2) fine timing delay 3) falling edge adjust all 3 delay functions are independent of each other, and independent for each channel. the programming of the delay functions is done using a 16 bit register, loaded serially, which contains both a de- lay and an address value. coarse delay coarse propagation delay adjustment is accomplished using a series of gate delays and multiplexers (see fig- ure 1). coarse delay provides a total delay span of: 1 coarse lsb = 90 ps 2 coarse lsb = 180 ps 4 coarse lsb = 360 ps 8 coarse lsb = 720 ps 16 coarse lsb = 1.44 ns 32 coarse lsb = 2.88 ns 0 ns coarse delay range 5.67 ns each channel has its own unique coarse delay setting and may be programmed independently from all other chan- nels. the coarse delay of any channel will not affect the fine delay of that channel, nor will it affect the overall delay of any other channel. the propagation delay of a rising edge and falling edge will track each other over the entire coarse delay span. (adding or subtracting coarse delay does not cause pulse width distortion.) lsb msb 0 1 2 3 4 5 16 bit serial register coarse delay register 90 ps 180 ps 360 ps 720 ps 1.44 ns 2.88 ns figure 1. coarse delay architecture e d o c y a l e d 0 0 0 0 0 0y a l e d m u m i n i ms n 0 . 0 1 1 1 1 1 1y a l e d m u m i x a ms n 7 6 . 5
5 ? 2005 semtech corp. rev. 3, 8/1/05 www.semtech.com test and measurement products edge629 fine delay select the fine delay section may be selected or bypassed by a multiplexer (see figure 2). if sfd (select fine delay) is high, fine delay will be used. if sfd is low, fine delay will be bypassed. fine delay dac outputs dac_fine_(0 3) are analog voltage outputs from the on- board dacs which program the fine delay elements of each channel. dac_fine_(0-3) pins are for test purposes only. nothing should be connected to these pins. circuit description (continued) fine delay fine delay is accomplished using an analog delay cell and an on-chip 6 bit dac (see figure 2). the fine delay range is designed to be ~2x the coarse delay resolution. fine delay provides a total delay span of: lsb 1 fine lsb = 2.5 ps (see note) 2 fine lsb = 5 ps 4 fine lsb = 10 ps 8 fine lsb = 20 ps 16 fine lsb = 40 ps msp 32 fine lsb = 80 ps 0 ns fine delay range 157.5 ps. note: because the transfer function is non-linear, some lsb steps could be as large as 5 ps. each channel has its own unique delay setting and may be programmed independently from all other channels. the fine delay of any channel will not affect the coarse delay of that channel, nor will it affect the overall delay of any other channel. the propagation delay of a rising and falling edge will track each other over the entire span of fine delay. (adding or subtracting fine delay will not cause pulse width distor- tion.) figure 2. fine delay architecture 6 bit dac sfd ? t e d o c c a dd f sy a l e d x x x x x x0 d e s s a p y b y a l e d e n i f 0 0 0 0 0 01 ) s n 0 . 0 ( y a l e d m u m i n i m 1 1 1 1 1 11 ) s p 7 5 1 ( y a l e d m u m i x a m
6 test and measurement products edge629 ? 2005 semtech corp. rev. 3, 8/1/05 www.semtech.com circuit description (continued) falling edge adjustment the falling edge of a signal may be adjusted to compen- sate for any system level pulse width distortion that may occur. falling edge adjust (fea) is accomplished using an analog delay cell and an on-chip 7 bit dac (see figure 3). fea may be bypassed completely by a multiplexer. also, fea affects only the propagation delay of the falling edge. it has no effect on the propagation delay of a rising edge. each channel has its own unique fea setting and may be programmed independently from all other channels. the fea of any channel will not affect the propagation delay of any other channel, nor will fea affect the propagation delay of a rising edge. there is a limitation on fea range vs. pulse width. falling edge adjust dac outputs dac_fall_(0 3) are analog voltage outputs from the on- board dacs which program the falling edge delay elements of each channel. dac_fall_(0-3) pins are for test purposes only. nothing should be connected to these pins. thermal monitor the edge629 features a thermal diode string consisting of 5 diodes as shown in figure 4 below. this string allows accurate die temperature measurements. figure 4. thermal diode string when an external bias current of up to 100 a is injected through the string, the voltage measured across the an- ode and cathode pins maps directly to the edge629 junction temperature (see figure 5). 7 bit dac sfe ? t figure 3. falling edge adjust architecture anode cathode temperature coefficient = 7.8 mv/ ? c bias current e f se d o c c a d e g d e g n i l l a f y a l e d n o i t u l o s e r 0x x x x x x xd e s s a p y b a e fa / n 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 s p 0 5 2 s p 0 5 2 + s p 5 . 2 s p 5 . 2 h t d i w e s l u p t u p n ie g n a r a e f s n 0 . 1s p 0 5 2 s p 0 0 9s p 0 5 2 s p 0 0 8s p 0 5 2 s p 0 0 7s p 0 5 2 s p 0 0 6s p 0 0 2 s p 0 0 5s p 0 0 1
7 ? 2005 semtech corp. rev. 3, 8/1/05 www.semtech.com test and measurement products edge629 circuit description (continued) programming the edge629 is programmed serially with 3 control lines: sdi serial data input cs chip select update register update which are all synchronous with ck. with cs valid (high), rising edge of ck will load sdi into the 16 bit shift register. with cs valid and update valid (high), ck high will make the selected latch go transparent. the falling edge of ck will then latch the data (see figures 6 and 7). data and address information are combined in the 16 bit word. bits 0 6 are used for data, bits 11 15 for address. bits 11 14 select 1 of 16 destinations, bit 15, if high, selects all 16 locations to be loaded simultaneously (use- ful for preloading all registers to a default state). figure 5. voltage vs. temperature for thermal diode string 4.20 4.00 3.80 3.60 3.40 3.20 3.00 2.80 2.60 2.40 2.20 0.00 50.0 100 150 temp ( ? c) v = v anode v cathode [v] : i force = 100 /anode : i force = 10 /anode : i force = 1 /anode v = v anode v cathode ; v cathode = vee t i b5 14 13 12 11 10 1 - d a r d a l3 a2 a1 a0 an o i t c n u f y a l e d 0 00000x y a l e d e s r a o c , 0 l e n n a h c 1 000011 y a l e d e n i f , 0 l e n n a h c 2 000101 t s u j d a e g d e g n i l l a f , 0 l e n n a h c 3 00011x d e s u t o n 4 00100x y a l e d e s r a o c , 1 l e n n a h c 5 001011 y a l e d e n i f , 1 l e n n a h c 6 001101 t s u j d a e g d e g n i l l a f , 1 l e n n a h c 7 00111x d e s u t o n 8 01000x y a l e d e s r a o c , 2 l e n n a h c 9 010011 y a l e d e n i f , 2 l e n n a h c a 010101 t s u j d a e g d e g n i l l a f , 2 l e n n a h c b 01011x d e s u t o n c 01100x y a l e d e s r a o c , 3 l e n n a h c d 011011 y a l e d e n i f , 3 l e n n a h c e 011101 t s u j d a e g d e g n i l l a f , 3 l e n n a h c f 01111x d e s u t o n x 1xxxx0 y a l e d e s r a o c , s l e n n a h c l l a x 1xxxx1 s n o i t c n u f l l a , s l e n n a h c l l a
8 test and measurement products edge629 ? 2005 semtech corp. rev. 3, 8/1/05 www.semtech.com circuit description (continued) figure 6. synchronous loading cd0 cd1 cd2 cd3 cd4 cd5 sfd a1 a0 fe0 fe1 fe2 fe3 fe4 fe5 fe6 a1 a0 ck0 ck15 load all load all ck sdi sdi sdi update coarse delay update fine delay update falling edge adjust update update selected delay register ... ... 629 digital interface timing 16 bit loads a2 a3 la fd0 fd1 fd2 fd3 fd4 fd5 sfe a1 a0 load all a2 a3 la a2 a3 la cs
9 ? 2005 semtech corp. rev. 3, 8/1/05 www.semtech.com test and measurement products edge629 circuit description (continued) figure 7. data interface address 15 14 13 12 11109876543210 a2 a3 la a1 a0 10 4 5 3210 fine delay msb sfd lsb 10 4 5 321 6 0 falling edge adjust msb sfe lsb 543210 coarse delay msb lsb channel 0 0 1 2 10 4 5 3210 fine delay msb sfd lsb 10 4 5 321 6 0 falling edge adjust msb sfe lsb 543210 coarse delay msb lsb channel 1 channel 2 channel 3 c d e . . . . . . . . . . . . . . . . . . update cs ck sdi
10 test and measurement products edge629 ? 2005 semtech corp. rev. 3, 8/1/05 www.semtech.com circuit description (continued) timing inputs in/in* and in0/in0* in3/in3* are high speed differen- tial inputs which require >300 mv of differential input voltage for reliable switching. these inputs may receive differential input signals with amplitudes up to 3.3v. this wide range input voltage com- pliance allows cmos signals to drive the edge629 directly. the inputs may go all the way up to vcc and still not cause any saturation. the edge629 will operate at full performance under these input conditions. do not leave any differential inputs floating as they will be in an indeterminate state. all unused inputs must be tied to either a high or low level. connecting unused timing inputs to vcc is an acceptable method to make an input high. however, to make an input low, it must be con- nected to vee +2.0v or higher. input mux select each delay channel can select its input from one of two sources. if mux select is high (sel > sel*), in/in* will be selected for all four channels. if mux select is low (sel < sel*), in0/in0* in3/in3* will be selected for each channel. sel/sel* have internal pull-up/pull-down resistors which, when left floating, place the chip in fanout mode. data interface digital inputs all data digital inputs are standard, single ended ecl in- puts with v bb = 1.3v relative to vcc. however, all digital inputs may receive input signals anywhere between vcc and vee. this wide input voltage compliance allows cmos signals to program the edge629 without causing satura- tion problems. all digital interface inputs are "3.3v rail to rail" cmos compatible provided vcc = +3.3v and vee = ?v. ck, sdi, and update all have an internal pull-down resis- tor network to establish a default condition of a logical 0 when left floating. cs has a large (~50 k ? ) internal pull- up resistor to vcc to establish a default condition of a logical 1 when left floating. for optimal performance, all data interface digital inputs should be static when the edge 629 is actively delaying signals. (however, it is acceptable if ck continues to run.) timing outputs out0/out0* ?out3/out3* are standard differential ecl open emitter outputs. compensation pins comp0, comp1, comp2, and comp3 are op amp compensation pins requiring external 100 pf capacitors to vee. sel* vcc sel 50k ? 50k ? vee vcc ck, sdi, update vcc cs vee vcc 50k ? 50k ? 50k ? * l e s / l e se c r u o s t u p n ie d o m 0* 3 n i / 3 n i * 0 n i / 0 n ih g u o r h t s s a p 1* n i / n it u o n a f
11 ? 2005 semtech corp. rev. 3, 8/1/05 www.semtech.com test and measurement products edge629 package information pin descriptions 64-pin tqfp 10 mm x 10 mm x 1.4 mm d e d 1 e 1 a b d n 1 exposed heatsink 3.56 .50 dia. 12 typ. ? 12 typ. ? a a 2 a 1 a l a 1 b .17 max .25 c lead complanarity seating plane standoff ddd m c a b s d s ccc c .20 rad. typ. 20 rad. typ. 6 ? 4 ? notes: 1. all dimensions in millimeters. 2. dimensions shown are nominal with tolerances as indicated. 3. l/f: eftec 64t copper or equivalent, 0.127mm (.005 ) or 0.15mm (.006 ) thick. 4. foot length l is measured at gage plane, at 0.25 above the seating plane. . s m i de c n a r e l o te u l a v a. x a m0 6 . 1 1 ax a m 5 1 . / . n i m 5 0 . 2 a5 0 . 0 4 . 1 d0 2 . 0 0 . 2 1 1 d0 1 . 0 0 . 0 1 e0 2 . 0 0 . 2 1 1 e0 1 . 0 0 . 0 1 l0 1 . / 5 1 . +0 6 . ec i s a b0 5 . b5 0 . 2 2 . ? 7 - ? 0 d d d. x a m8 0 . c c c. x a m8 0 . s s e n k c i h t e g a k c a p0 4 . 1 t n i r p t o o fm m 2 + y d o b top view
12 test and measurement products edge629 ? 2005 semtech corp. rev. 3, 8/1/05 www.semtech.com recommended operating conditions absolute maximum ratings stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these, or any other conditions beyond those listed, is not implied. exposure to absolute maximum conditions for extended periods may affect device reliability. r e t e m a r a pl o b m y sn i mp y tx a ms t i n u y l p p u s r e w o p l a t o te e v c c v2 . 42 . 55 . 5 +v e r u t a r e p m e t n o i t c n u jj t0 0 0 1 +c ? r e t e m a r a pl o b m y sn i mp y tx a ms t i n u y l p p u s r e w o pe e v c c v0 0 . 7v n i p t u p n i l a t i g i d y n a n o e g a t l o v 5 . 0 e e v5 . 0 + c c vv n i p t u p n i g o l a n a y n a n o e g a t l o v 5 . 0 e e v5 . 0 + c c vv t n e r r u c t u p t u o0 5 a m e r u t a r e p m e t e g a r o t ss t5 6 0 5 1 +c ? e r u t a r e p m e t n o i t c n u jj t0 5 1 +c ? e r u t a r e p m e t g n i r e d l o s ) n i p e h t m o r f " 5 2 . , s d n o c e s 5 ( l o s t0 6 2 +c ? c j ) e s a c f o p o t o t ( c j 5 . 1c ? a j ) r i a l l i t s @ ( a j 8 2c ? a j ) m p f l 0 0 4 @ ( a j 1 2c ?
13 ? 2005 semtech corp. rev. 3, 8/1/05 www.semtech.com test and measurement products edge629 dc characteristics r e t e m a r a pl o b m y sn i mp y tx a ms t i n u s t u p n i g n i m i t ) * 3 n i / 3 n i * 0 n i / 0 n i , * n i / n i ( e g a t l o v t u p n i l a i t n e r e f f i d| * n i n i |3 .e e v c c vv e g n a r e g a t l o v h g i h t u p n ih i v0 . 2 + e e vc c vv e g n a r e g a t l o v w o l t u p n il i v0 . 2 + e e v3 . h i vv t n e r r u c h g i h t u p n ih i i0 0 1 0 0 1 +a t n e r r u c w o l t u p n il i i0 0 1 0 0 1 +a ) * l e s / l e s ( t u p n i t c e l e s e g a t l o v h g i h t u p n i* l e s l e s3 .e e v c c vv e g a t l o v w o l t u p n il e s * l e s3 .e e v c c vv e g n a r e d o m n o m m o c h g i h t u p n ih i v0 . 2 + e e vc c vv e g n a r e d o m n o m m o c w o l t u p n il i v0 . 2 + e e v3 . h i vv t n e r r u c h g i h t u p n ih i i0 5 2a t n e r r u c w o l t u p n il i i0 5 2a ) i d s , s c , e t a d p u , k c ( s t u p n i g n i m m a r g o r p e g a t l o v h g i h t u p n ih i v1 . 1 c c vc c vv e g a t l o v w o l t u p n il i v0 . 2 + e e v5 . 1 c c vv t n e r r u c h g i h t u p n ih i i0 5 2a t n e r r u c w o l t u p n il i i0 5 2a s t u p t u o l a t i g i d e g a t l o v h g i h t u p t u o l a t i g i d* t u o t u o0 0 60 9 6v m e g a t l o v w o l t u p t u o l a t i g i dt u o * t u o0 0 60 9 6v m e g n a r e d o m n o m m o c t u p t u o* t u o + t u o 2 5 . 1 c c v3 . 1 c c v1 . 1 c c vv t n e r r u c t u p t u ot u o i0 3a m t n e r r u c y l p p u s r e w o p v 2 . 4 = e e v c c ve e i1 6 50 0 9a m v 2 . 5 = e e v c c ve e i4 0 60 0 9a m v 5 . 5 = e e v c c ve e i3 1 60 0 9a m
14 test and measurement products edge629 ? 2005 semtech corp. rev. 3, 8/1/05 www.semtech.com ac characteristics test conditions (unless otherwise specified): "recommended operating conditions." r e t e m a r a pl o b m y sn i mp y tx a ms t i n u s t u p t u o / s t u p n i g n i m i t ) 2 e t o n ( y a l e d n o i t a g a p o r p m u m i n i m ) 3 , 0 ( t u o o t n i ) 3 , 0 ( t u o o t 3 , 0 n i ? 0 = d f o t d e l b a s i d d f , d p t ? 0 = a e f o t d e l b a s i d a e f , d p t n i m d p t n i m d p t ? d p t ? d p t 2 8 2 . 1 6 0 4 . 1 7 5 3 . 1 1 8 4 . 1 0 2 3 0 5 9 2 3 4 . 1 6 5 5 . 1 s n s n s p s p n o i t a g a p o r p e g d e g n i l l a f / e g d e g n i s i r ) d e l b a s i d a e f ( e c n e r e f f i d y a l e d | d p t + d p t | 30 1s p ) 2 e t o n ( w e k s l e n n a h c - o t - l e n n a h c ) e d o m t u o n a f ( ) 3 , 0 ( t u o o t n i ) 3 , 0 ( t u o o t ) 3 , 0 ( n i 1 w e k s t 2 w e k s t 0 1 5 1 5 4 0 5 s p s p ) 2 e t o n ( y a l e d e l b a m m a r g o r p y a l e d e s r a o c y a l e d e n i f e s r a o c _ n a p s t e n i f _ n a p s t 5 . 5 0 1 1 0 . 6 0 5 1 5 . 6 0 8 1 s n s p ) 1 e t o n ( ) 1 = e f s ( t s u j d a e g d e g n i l l a fa e f0 0 2 0 5 2 0 0 3 s p ) 3 e t o n ( e z i s p e t s y a l e d e l b a m m a r g o r p y a l e d e s r a o c y a l e d e n i f t s u j d a e g d e g n i l l a f e s r a o c _ p e t s t e n i f _ p e t s t a e f _ p e t s t 0 . 1 0 . 1 0 . 1 5 9 5 5 0 1 1 7 7 s p s p s p ) d e l b a n e a e f ( y c n e u q e r f g n i t a r e p o m u m i x a mx a m f0 . 1z h g ) d e l b a s i d a e f ( y c n e u q e r f g n i t a r e p o m u m i x a mx a m f3 . 1z h g ) s t u p t u o t a ( h t d i w e s l u p m u m i n i mn i m w p0 5 3s p ) % 0 8 - % 0 2 ( s e m i t l l a f d n a e s i r t u p t u of t / r t0 1 10 5 1s p ) p m e t e i d . s v ( t n e i c i f f e o c e r u t a r e p m e t d e l b a s i d a e f & d f , n i m = d c d e l b a s i d a e f & d f , x a m = d c d e l b a s i d a e f , n i m = d f & d c d e l b a s i d a e f , x a m = d f & d c n i m = a e f & , d f , d c x a m = a e f & , d f , d c ? / d p t ? t 4 . 2 3 . 3 1 3 . 3 1 . 5 1 2 . 5 8 . 8 1 c ? / s p c ? / s p c ? / s p c ? / s p c ? / s p c ? / s p r o r r e g n i m i t l a t o t ? y c n e u q e r f . s v d p t k l a t s s o r c l e n n a h c - o t - l e n n a h c ? e l c y c y t u d . s v d p t y a l e d m u m i n i m @ r e t t i j y a l e d m u m i x a m @ r e t t i j 0 2 2 0 2 0 1 1 5 s p s p s p s p
15 ? 2005 semtech corp. rev. 3, 8/1/05 www.semtech.com test and measurement products edge629 ac characteristics (continued) test conditions (unless otherwise specified): "recommended operating conditions." ac characteristics are guaranteed by design and characterization. not production tested. r e t e m a r a p l o b m y sn i mp y tx a ms t i n u e c a f r e t n i a t a d e m i t p u t e s k c o t i d s k c o t s c k c o t e t a d p u u s t u s t u s t 0 1 0 1 0 2 s n s n s n e m i t d l o h k c i d s o t k c s c o t k c e t a d p u o t h t h t h t 4 4 4 s n s n s n s h t d i w e s l u p m u m i n i m h g i h k c w o l k c d o i r e p k ct 3 1 3 1 0 3 s n s n s n e m i t g n i l t t e s c a d 1s test conditions (unless otherwise specified): "recommended operating conditions." note 1: tested with an input pulse = 50 ns. this parameter is guaranteed by characterization for input pulse widths 700 ps. note 2: coarse delay = 0, fine delay and falling edge adjust disabled. case temperature = 50 ? c. note 3: coarse delay is monotonic. fine delay is monotonic. since the fine delay spans close to 2 lsbs of coarse delay, the summation of digital codes for coarse and fine delays is not monotonic. proper binary searching using both the coarse and fine delays is achieved first with the coarse (with sfd=1), and then with the fine delays as separate searches.
16 test and measurement products edge629 ? 2005 semtech corp. rev. 3, 8/1/05 www.semtech.com ordering infor mation contact infor mation semtech corporation test and measurement division 10021 willow creek rd., san diego, ca 92131 phone: (858)695-1808 fax (858)695-2633 r e b m u n l e d o me g a k c a p f x a 9 2 6 e p f q t m m 4 . 1 x 0 1 x 0 1 p o t n o k n i s t a e h d e s o p x e / w f x a 9 2 6 m v ed r a o b n o i t a u l a v e 9 2 6 e g d e

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